Computing power of Central Processing Units (CPU) has dramatically increased in the last few decades, supported by both miniaturization and increasing clock frequencies. More and more electronic gates are being packed onto the same area of a silicon die as miniaturization advances. More hardware supported parallel computing, pipelining for example, has further increased the computing power of CPUs.
Frequency increases have sped up CPUs even more directly and linearly. But the long predicted physical limit of the miniaturization process seems to have finally been reached recently, so that increasing the frequency appears to be no longer feasible due to the accompanied non-linear increase of power consumption, even though miniaturization still continues today. This situation has forced the industry to go toward packing multiple CPU cores onto the same silicon die without increasing clock frequency. Parallel computing has emerged from an optional computational architecture for supercomputing into the mainstream choice for general computing, and this will likely continue in the future. As a result of this fundamental computing architecture change, algorithm design, data structure design, and programming strategies are all facing new challenges.